1. Field of the Invention
The present invention relates to a semiconductor storage circuit. In particular, the present invention relates to a semiconductor storage circuit that stores data of two bits in one memory cell.
2. Description of the Related Art
A conventional semiconductor storage circuit that stores data of two bits in one memory cell has been suggested (for example, refer to Japanese Patent Application Laid-Open (JP-A) No. 2006-309811). When data is read in a non-volatile semiconductor storage circuit, represented by a flash memory, a logical level of read data is determined based on a current value of a memory cell of a read object. A circuit that determines a logical level based on a distribution of memory cell current values between logical levels or a current difference (hereinafter, referred to as current window), is called a sense amplifier. A current of the memory cell of the read object flows into the sense amplifier through a connected bit line.
FIG. 21 is a block diagram showing the schematic configuration of a conventional NOR-type semiconductor storage circuit 1000 that stores data of two bits in one memory cell, which has been described in JP-A No. 2006-309811. FIG. 22 is a circuit diagram of a memory cell array 110 and a multiplexer 120 of the semiconductor storage circuit 1000. As shown in FIG. 21 and FIG. 22, the semiconductor storage circuit 1000 is configured to include the memory cell array 110, the multiplexer 120, and a sense amplifier 130. The sense amplifier 130 includes two sense amplifiers SA0 and SA1. The memory cell array 110 is configured to use multi-bit-type memory cells.
COMMMON is a common voltage source of the memory cells. DS [4M−1:0] are signals to select a sub-bit line connected to COMMON. SS [2M−1:0] are signals to select a sub-bit line connected to a main bit line. Y [J−1:0] are signals to select a main bit line connected to the sense amplifier. WL [N×M−1:0] are word lines. ICELL0 and ICELL1, shown in FIG. 23 to be described below, are current values of the memory cells of the read objects. ICELL0 and ICELL1 flows into the sense amplifier SA0 and the sense amplifier SA1, respectively. The sense amplifier SA0 and the sense amplifier SA1 determine the logical levels of the memory cells of the read objects, based on the current values ICELL0 and ICELL1, and output the logical levels to DOUT0 and DOUT1, respectively.
In this case, M is the number of memory cell arrays 110. N is the number of word lines that are included in each memory cell array 110. J is the number of main bit line selection signals Y. SBL [2(J+1):0] are sub-bit lines and MBL [J:0] are main bit lines. The M memory cell arrays 110 are connected to MBL [J:0]. However, FIG. 22 shows only one of the M memory cell arrays 110, and the sub-bit lines and the main bit lines are shown until SBL [8:0] and MBL [3:0], respectively.
Each memory cell array 110 is connected to terminals of the signals DS and SS to select the sub-bit lines not overlapped to other signal lines, to select the sub-bit lines included in each memory cell array. Note that, a transistor where “MC” is added as a prefix is a multi-bit-type memory cell. A transistor where “MD” is added as a prefix is a transistor (drain selector) to select the sub-bit line connected to COMMON, and a gate terminal thereof receives the sub-bit line selection signal DS (drain selection signal). The transistor where “MS” is added as a prefix is a transistor (source selector) to select the sub-bit line connected to the main bit line, and a gate terminal thereof receives the sub-bit line selection signal SS (source selection signal). A transistor where “MY” is added as a prefix is a transistor to select the main bit line connected to the sense amplifier, the main bit line selection signal Y is received in a gate terminal thereof.
As shown in the memory cell array 110, in the memory cell array of the NOR-type semiconductor storage circuit, plural word lines that are connected to the gate terminals of the memory cells and plural bit lines that are connected to the source terminals or the drain terminals (hereinafter, referred to as diffusion layers) are disposed in a matrix. The memory cells are disposed on intersections of the word lines and the bit lines, respectively. In this case, selection of the memory cell where data is read is realized by selecting the word line connected to the gate terminal of the memory cell, connecting the bit line connected to one diffusion layer to the sense amplifier, and connecting the other diffusion layer to COMMON.
A direction in which a memory cell current flows is different, according to which of the two diffusion layers of the memory cell is connected to the sense amplifier. The multi-bit-type memory cell of the memory cell array 110 may be adjusted to have a current value different according to each current direction. Thereby, the multi-bit-type memory cell realizes read of data of two bits or more. Here, it is assumed that the two diffusion layers of the memory cell are diffusion layers of the L side and the R side, respectively, and the side connected to the sense amplifier is a data read object. For example, when the L side of MC00 is connected to the sense amplifier, MC00_L becomes a data read object.
FIG. 23 and FIG. 24 are explanatory diagrams showing a data read operation of the semiconductor storage circuit 1000. Note that, FIG. 23 and FIG. 24 show only one of the M memory cell arrays 110 and one word line WL0 of the N word lines. The operation of the semiconductor storage circuit 1000 will be described using FIG. 23 and FIG. 24.
Referring to FIG. 23, the case where MC00_R and MC03_L are selected, will be described.
By selecting WL0 from the memory cell array 110, all of the memory cells including MC00 and MC03, which the gate terminal are connected to WL0, enter in a conductive state. By selecting DS0, MD00 and MD01 enter in a conductive state. Then, COMMON is connected to the diffusion layers of the MC00_L side and the MC03_R side through SBL0 and SBL4.
By selecting SS0, MS00 and MS01 enter in a conductive state. Then, MBL0 and the MBL1 are connected to the diffusion layers of the MC00_R side and the MC03_L side through SBL1 and SBL3. By selecting Y0, MY00 and MY01 of the multiplexer 120 enter in a conductive state. Then, MBL0 and MBL1 are connected to the sense amplifiers SA0 and SA1, respectively.
Thereby, MC00_R and MC03_L are selected, and currents ICELL0 and ICELL1 flow into the sense amplifiers SA0 and SA1, respectively. The sense amplifier SA0 and the sense amplifier SA1 output logical levels, which are determined on the basis of the currents ICELL0 and ICELL1, to DOUT0 and DOUT1, respectively.
Referring to FIG. 24, the case where MC03_R and MC06_L are selected, will be described.
By selecting WL0 from the memory cell array 110, all of the memory cells including MC03 and MC06, which the gate terminal are connect to WL0, enter in a conductive state. By selecting DS3, MD30 and MD31 enter in a conductive state. Then, COMMON is connected to the diffusion layers of the MC03_L side and the MC06_R side through SBL3 and SBL7.
By selecting SS1, MS11 and MS12 enter in a conductive state. Then, MBL1 and MBL2 are connected to the diffusion layers of the MC03_R side and the MC06_L side through SBL4 and SBL6. By selecting Y1, MY10 and MY11 of the multiplexer 120 enter in a conductive state. Then, MBL1 and MBL2 are connected to the sense amplifiers SA0 and SA1, respectively.
Thereby, MC03_R and MC06_L are selected, and the currents ICELL0 and ICELL1 flow into the sense amplifier SA0 and the sense amplifier SA1, respectively. The sense amplifier SA0 and the sense amplifier SA1 output logical levels, which are determined on the basis of the currents ICELL0 and ICELL1, to DOUT0 and DOUT1, respectively.
Here, when the (2α+β)-th SS (α is 0, 1, 2, . . . , and M−1 and β=0, 1) and the even-numbered Y are selected, the ((2α+0)×2+β)-th DS is selected. Thus, when the odd-numbered Y is selected, ((2α+1)×2+β)-th DS is selected.
Accordingly, the conventional semiconductor storage circuit 1000 simultaneously selects a pair of main bit lines adjacent to each other, and connects the main bit lines to the sense amplifiers, respectively. The sense amplifier SA0 reads and uses data of the R side of the memory cell, such as MC00_R and MC03_R. The sense amplifier SA1 reads and uses data of the L side of the memory cell, such as MC03_L and MC06_L. Therefore, in the semiconductor storage circuit 1000, the different sense amplifiers read and use the different data of the L side and the R side, even in the same memory cell, such as MC03_L and MC03_R.
The memory cell current value is affected by the logical level of the non-selection side of the same memory cell. For example, a memory cell current value of MC00_L is affected by a logical level of MC00_R. Likewise, a memory cell current value of MC00_R is affected by a logical level of MC00_L. The logical level of the non-selection side affects the memory cell current value like resistance. A resistance value thereof is large when a logical level is “0” and is small when the logical level is “1.” Therefore, as shown in FIG. 25A, when the logical level of the non-selection side is “0,” the memory cell current value is distributed with a small current value, and when the logical level of the non-selection side is “1,” the memory cell current value is distributed with a large current value. Since a small current value is preferable at the time of determining the logical level of “0,” the logical level of the non-selection side is preferably “0” at the time of reading the logical level of “0.” Likewise, since a large current value is preferable at the time of determining the logical level of “1,” the logical level of the non-selection side is preferably “1” at the time of reading the logical level of “1.”
Meanwhile, a characteristic of the sense amplifier is changed due to the process change. Thereby, a threshold value of the memory cell current value that is used to determine the logical level is different for each sense amplifier. For example, in the case where data is read by the sense amplifiers having characteristics shown in FIG. 25B and FIG. 25C, the sense amplifier of FIG. 25B may not determine the logical level as “0” when the current value is not small, and the sense amplifier of FIG. 25C may not determine the logical level as “1” when the current value is not large.
As shown in FIG. 26A, the case where MCXX_L and MCXX_R have the logical levels “0” and “1,” respectively, will be described. Note that MCXX may be any memory cell in the memory cell array 110.
In FIG. 26B, a case where characteristics of the sense amplifier SA0 and the sense amplifier SA1 are as shown in FIG. 25B and FIG. 25C, when reading out data from MCXX_L including a data of logical level “0”. Due to the characteristic change of the sense amplifier SA1, the threshold value of the memory cell current value to determine the logical level is decreased from A to A′. Further, due to the characteristic change of the sense amplifier SA0, the current value of MCXX_R is distributed with a relatively large current value. Accordingly, the memory cell current value of the logical level “0” is distributed as shown in (2) of FIG. 26B. When a gap between A′ and (2) decreases, a data read characteristic of the logical level “0” deteriorates.
In FIG. 26C, a case where characteristics of the sense amplifier SA0 and the sense amplifier SA1 are as shown in FIG. 25B and FIG. 25C, when reading out data from MCXX_R including a data of logical level “1”. Due to the characteristic change of the sense amplifier SA0, the threshold value of the memory cell current value to determine the logical level is increased from A to A′. Further, due to the characteristic change of the sense amplifier SA1, the current value of MCXX_L is distributed with a relatively small current value. Accordingly, the memory cell current value of the logical level “1” is distributed with as shown in (4) of FIG. 26C. When a gap between of A′ and (4) decreases, a data read characteristic of the logical level “1” deteriorates.